Efficient Design & Analysis of Phase Locked Loop Using High Performance Voltage Control Oscillator with Four Outputs for Communication Standard Applications

Abstract

Phase Locked Loop (PLL) with multiple outputs in low power and high speed is designed with 45nm size IC’s. Proposed PLL is designed using BSIM4 model for n and p channel CMOS transistor which is supported by microwind 3.1 VLSI software. To obtain the layout of proposed PLL, CMOS circuit of each element of proposed PLL is converted into physical layout using lambda based rules of microwind 3.1 software. After cascading the layout of each element, final layout is obtained. This paper particularly focuses on analysis and design of phase-locked loop with low power consumption with high performance using VLSI technology. When compared to conventional design, here focus is made on VCO. The input  frequency is collected from  external source which is used to generate four frequencies provided for the circuits of communication standard in high-speed Integrated Circuits.