A Transient Enhanced Capacitor-less Low dropout Regulator Using 180nm CMOS technology

Abstract

Demand for system on-chip (SoC) designs and portable electronics has risen quickly in recent years. The dual loop architecture serves as the foundation for the capacitorless LDO described in this research. In order to overcome the difficulties in establishing stability, including quick transient performance and minimal voltage spikes under rapid loadcurrent fluctuations, the regulator uses two feedback loops. The suggested design runs with a 0-100 pF capacitive load and does not require a decoupling capacitor to be placed at the output. A 0.18 µm CMOS technology is used for performing the simulations on the design. The Capacitor-less LDO is given an input voltage of 1.0 - 1.4V, and it gives an output of 0.9 V. Line and Load Regulation obtained are 0.821 mV/V and 0.1122 mA/V respectively. The Capacitor-less LDO has a phase margin of 87.55^o , making it more stable whereas phase margin of Conventional LDO is just 43.78^o . The transient response of Capacitor less LDO is enhanced succesfully. The overshoot and undershoot of the Capacitorless LDO are 16.38 mV and 16.9 mV respectively while the conventional LDO shows 27 mV and 33.6 mV respectively. Settling time of Capacitor-less LDO is 1.54 µs, which is much better than settling time of conventional LDO, which is 8 µs