A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC)

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Architecture of Network-on-Chip
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Published: Jan 31, 2023
DOI: https://doi.org/10.17762/ijritcc.v11i2s.6032
Keywords:
Integrated Shortest Path Search Algorithm (ISPSA), Mesh Topology, Network-on-Chip (NoC), Internet Protocol

Main Article Content

S. Karthick
Department of Electronics and Communication Engineering Veltech Rangarajan Dr.Sagunthala R&D Institute of Science and Technology Chennai-600062, Tamil Nadu, India
P. Vijay Shankar
Department of Electrical and Electronics Engineering Geethanjali College of Engineering and Technology Hyderabad, Telangana-501301
T. Jayakumar
Department of Electrical and Electronics Engineering Nandha Engineering College Erode, Tamilnadu -638052 India
G. Merlin Suba
Department of Electrical and Electronics Engineering Panimalar Engineering College Poonamallee, Chennai, Tamil Nadu 600123
Munleef Quadir
Department of Computer Science, College of Computer Science and Information Technology , Jazan University, Jazan, Kingdom of Saudi Arabia
A. Thomas Paul Roy
Department of Computer Science and Engineering PSNA College of Engineering & Technology Kothandaraman Nagar, Tamil Nadu 624622

Abstract

A novel data dispatching or communication technique based on circulating networks of any network IP is suggested for multi data transmission in multiprocessor systems using Networks-On-Chip (NoC). In wireless communication network management have some negatives have heavy data losses and traffic of data sending data while packet scheduling and low performance in the varied network due to workloads. To overcome the drawbacks, in this method proposed system is Integrated Shortest Path Search Algorithm (ISPSA) using mesh topologies. The message is sent to IP (Internet Protocol) in the network until the specified bus accepts it. Integrated Shortest Path Search Algorithm for communication between two nodes is possible at any one moment. On-chip wireless communications operating at specific frequencies are the most capable option for overcoming metal interconnects multi-hop delay and excessive power consumption in Network-on-Chip (NoC) devices. Each node can be indicated by a pair of coordinates (level, position), where the level is the tree's vertical level and the view point is its horizontal arrangement in the sequence of left to right. The output gateway node's n nodes are linked to two nodes in the following level, with all resource nodes located at the bottommost vertical level and the constraint of this topology is its narrow bisection area. The software Xilinx 14.5 tool by using that overall performance analysis of mesh topology, each method are reduced data losses with better accuracy although the productivity of the delay is decreased by 21 % was evaluated and calculated..

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How to Cite
Karthick, S. ., Shankar, P. V. ., Jayakumar, T. ., Suba, G. M. ., Quadir, M. ., & Paul Roy, A. T. . (2023). A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC). International Journal on Recent and Innovation Trends in Computing and Communication, 11(2s), 87–95. https://doi.org/10.17762/ijritcc.v11i2s.6032
Issue
Vol. 11 No. 2s (2023)
Section
Articles

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