Implementation of Low Power and Area Efficient 2-Bit/Step Asynchronous SAR ADC using Successively Activated Comparators

Abstract

A low power (0.4-09V) 2-Bit/Step successive approximation register (SAR) analog to digital converter (ADC) is conferred. A 2-Bit/Step operation technique is proposed which implementing a dynamic threshold configuring comparator instead of number of digital to analog converters (DACs). Area and power is reduced by successively activated comparators. Here the second comparator is activated reflecting the preceding comparator’s results. Because the second comparator threshold is configured dynamically for every cycle, only two comparators are required instead of three. By successively activating the comparators, the number of DAC settling is halved, so the power and area overhead is very small and the performance will be increased. The proposed ADC was implemented in a 90nm technology achieved a gain of 35.4 db, power of 0.89 ?w and the conversion time of 0.32ns with a supply voltage of 0.4v. The total core area of this ADC is 7.74 ?m2.