FPGA Implementation & Performance Comparision of Various High Speed unsigned Binary Multipliers using VHDL

Abstract

Today, most of the DSP computations involve the use of multiply accumulate operations and therefore the design of fast and efficient multipliers is imperative. The addition and multiplication of two binary numbers is the fundamental and most often used arithmetic operation in microprocessors, digital signal processors and data-processing application-specific integrated circuits. In this paper, we present the study of different types of multipliers by comparing the speed and area of each. In this work, VHDL coding and XILINX ISE Simulator is employed to implement multipliers like WTM, Dadda Multiplier, Vedic Multiplier, CSHM, Serial Multiplier and Multipliers using different compressors in Wallace tree architecture. The analysis of this work would be helpful to choose a better multiplier in order to fabricate an efficient system.