Design and Analysis of Multiplexer based Approximate Adder for Low Power Applications
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Abstract
Low power consumption is crucial for error-acceptable multimedia devices, with picture compression approaches leveraging various digital processing architectures and algorithms. Humans can assemble useful information from partially inaccurate outputs in many multimedia applications. As a result, producing exact outputs is not required. The demand for an exact outcome is fading because new innovative systems are forgiving of faults. In the domain where error-tolerance is accepted, approximate computing is a new paradigm that relaxes the requirement for an accurate modeling while offering power, time, and delay benefits. Adders are an essential arithmetic module for regulating power and memory usage in digital systems. The recent implementation and use of approximate adders have been supported by trade-off characteristics such as delay, lower power consumption. This study examines the delay and power consumption of conventional and approximate adders. Also, a simple, fast, and power-efficient multiplexer-based approximate adder is proposed, and its performance outperforms the adders compared with existing adders. The proposed adder can be utilized in error-tolerant and various digital signal processing applications where exact results are not required. The proposed and existing adders are designed using EDA software for the performance calculations. With a delay of 81 pS, the proposed adder circuit reduces power consumption compared to the exact one. The experiment shows that the designed approximate adder can be used to implement circuits for image processing systems because it has a smaller delay and uses less energy.
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References
Lee, Y. H., Kuei, C. H., Kao, Y. Z., & Fan Jiang, S. S. (2021). Algorithm and VLSI architecture designs of a lossless embedded compression encoder for HD video coding systems. Journal of Circuits, Systems and Computers, 30(04), 2130004.
Sasikumar, A., Subramaniyaswamy, V., Jannali, R., Rao, V. S., & Ravi, L. (2022). Design and area optimization of CMOS operational amplifier circuit using hybrid flower pollination algorithm for IoT end-node devices. Microprocessors and Microsystems, 93, 104610.
Chung, Y., & Kim, Y. (2021). Comparison of approximate computing with sobel edge detection. IEIE Transactions on Smart Processing & Computing, 10(4), 355-361.
Hasan, M., Siddique, A. H., Mondol, A. H., Hossain, M., Zaman, H. U., & Islam, S. (2021). Comprehensive study of 1-bit full adder cells: review, performance comparison and scalability analysis. SN Applied Sciences, 3(6), 644.
Pandey, D., Singh, S., Mishra, V., Satapathy, S., & Banerjee, D. S. (2021, May). Sam: A segmentation based approximate multiplier for error tolerant applications. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-5).
Mohammadi, A., Ghanatghestani, M. M., Molahosseini, A. S., & Mehrabani, Y. S. (2022). High-performance and energy-area efficient approximate full adder for error tolerant applications. ECS Journal of Solid State Science and Technology, 11(8), 081010.
Shin, H., Kang, M., & Kim, L. S. (2021, December). Fault-free: a fault-resilient deep neural network accelerator based on realistic reram devices. In 2021 58th ACM/IEEE Design Automation Conference (DAC) (pp. 1039-1044). IEEE
Sasikumar, A., Ravi, L., Kotecha, K., Indragandhi, V., & Subramaniyaswamy, V. (2022). Reconfigurable and hardware efficient adaptive quantization model-based accelerator for binarized neural network. Computers and Electrical Engineering, 102, 108302.
Liu, W., Zhang, T., McLarnon, E., O’Neill, M., Montuschi, P., & Lombardi, F. (2019). Design and analysis of majority logic-based approximate adders and multipliers. IEEE transactions on emerging topics in computing, 9(3), 1609-1624.
Nojehdeh, M. E., & Altun, M. (2020). Systematic synthesis of approximate adders and multipliers with accurate error calculations. Integration, 70, 99-107.
Jiang, H., Santiago, F. J. H., Mo, H., Liu, L., & Han, J. (2020). Approximate arithmetic circuits: A survey, characterization, and recent applications. Proceedings of the IEEE, 108(12), 2108-2135.
Bhattacharjya, R., Mishra, V., Singh, S., Goswami, K., & Banerjee, D. S. (2020, September). An approximate carry estimating simultaneous adder with rectification. In Proceedings of the 2020 on Great Lakes Symposium on VLSI (pp. 139-144).
Sato, T., Yang, T., & Ukezono, T. (2019). Trading accuracy for power with a configurable approximate adder. IEICE Transactions on Electronics, 102(4), 260-268.
Ramachandran, G., DIXIT, C. K., Kishore, K., & Arunraja, A. (2021, March). Performance analysis of mantissa multiplier and dadda tree multiplier and implementing with DSP architecture. In 2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS) (pp. 1583-1587).
Puchala, D. (2021). Approximate calculation of 8-point DCT for various scenarios of practical applications. EURASIP Journal on Image and Video Processing, 2021(1), 18.
Rizzo, R. G., & Calimera, A. (2019). Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection. Journal of Low Power Electronics and Applications, 9(2), 17.
Asaithambi, S., Rajappa, M., & Ravi, L. (2019). Optimization and control of CMOS analog integrated circuits for cyber-physical systems using hybrid grey wolf optimization algorithm. Journal of Intelligent & Fuzzy Systems, 36(5), 4235-4245.
Thakur, G., Sohal, H., & Jain, S. (2020, November). FPGA-based parallel prefix speculative adder for fast computation application. In 2020 Sixth International Conference on Parallel, Distributed and Grid Computing (PDGC) (pp. 206-210).
Khaksari, A., Akbari, O., & Ebrahimi, B. (2023). BEAD: Bounded error approximate adder with carry and sum speculations. Integration, 88, 353-361.
Kim, Y. (2019). An accuracy enhanced error tolerant adder with carry prediction for approximate computing. IEIE Transactions on Smart Processing & Computing, 8(4), 324-330.
Patel, S. K., Garg, B., & Rai, S. K. (2020). An efficient accuracy reconfigurable CLA adder designs using complementary logic. Journal of Electronic Testing, 36, 135-142.
Vaithiyanathan, D., Kolhe, R., Mishra, A. K., Britto, P. J., & Kunaraj, K. (2020, December). Performance Analysis of 8-Point Approximate DCT Architecture Using Conventional and Hybrid Adders. In 2020 IEEE International Symposium on Smart Electronic Systems (iSES)(Formerly iNiS) (pp. 246-249).
Nayar, R., Balasubramanian, P., & Maskell, D. L. (2020, July). Hardware optimized approximate adder with normal error distribution. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 84-89).
Vinod, G. U., Vineesh, V. S., Tudu, J. T., Fujita, M., & Singh, V. (2020, November). LUT-based circuit approximation with targeted error guarantees. In 2020 IEEE 29th Asian Test Symposium (ATS) (pp. 1-6).
Nagarajan, M., Sasikumar, A., Muralidharan, D., & Rajappa, M. (2020). Fixed point multi-bit approximate adder based convolutional neural network accelerator for digit classification inference. Journal of Intelligent & Fuzzy Systems, 39(6), 8521-8528.
Yin, P., Wang, C., Waris, H., Liu, W., Han, Y., & Lombardi, F. (2020). Design and analysis of energy-efficient dynamic range approximate logarithmic multipliers for machine learning. IEEE Transactions on Sustainable Computing, 6(4), 612-625.
V. Gupta, D. Mohapatra, A. Raghunathan and K. Roy, "Low-Power Digital Signal Processing Using Approximate Adders," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 124-137, Jan. 2013, doi: 10.1109/TCAD.2012.2217962.