A Brand-New, Area - Efficient Architecture for the FFT Algorithm Designed for Implementation of FPGAs

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Specifications of the RTL diagram for an 8-point fast Fourier transform processor
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Published: Mar 10, 2023
DOI: https://doi.org/10.17762/ijritcc.v11i2.6135
Keywords:
ECC, Cryptography, FFT processor, FPGA

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Gutti Naga Swetha
ECE department, Guru Nanak Dev Engineering College, Bidar, Karnataka, India
Anuradha M. Sandi
ECE department, Guru Nanak Dev Engineering College, Bidar, Karnataka, India

Abstract

Elliptic curve cryptography, which is more commonly referred to by its acronym ECC, is widely regarded as one of the most effective new forms of cryptography developed in recent times. This is primarily due to the fact that elliptic curve cryptography utilises excellent performance across a wide range of hardware configurations in addition to having shorter key lengths. A High Throughput Multiplier design was described for Elliptic Cryptographic applications that are dependent on concurrent computations. A Proposed (Carry-Select) Division Architecture is explained and proposed throughout the whole of this work. Because of the carry-select architecture that was discussed in this article, the functionality of the divider has been significantly enhanced. The adder carry chain is reduced in length by this design by a factor of two, however this comes at the expense of additional adders and control. When it comes to designs for high throughput FFT, the total number of butterfly units that are implemented is what determines the amount of space that is needed by an FFT processor. In addition to blocks that may either add or subtract numbers, each butterfly unit also features blocks that can multiply numbers. The size of the region that is covered by these dual mathematical blocks is decided by the bit resolution of the models. When the bit resolution is increased, the area will also increase. The standard FFT approach requires that each stage contain  times as many butterfly units as the stage before it. This requirement must be met before moving on to the next stage.

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How to Cite
Naga Swetha, G. ., & M. Sandi, A. . (2023). A Brand-New, Area - Efficient Architecture for the FFT Algorithm Designed for Implementation of FPGAs. International Journal on Recent and Innovation Trends in Computing and Communication, 11(2), 114–122. https://doi.org/10.17762/ijritcc.v11i2.6135
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Vol. 11 No. 2 (2023): February (2023) Issue
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