Efficient Circuit Configuration to Reduce Comparator Requirement of 8-Bit Flash Analog to Digital Convertor

Abstract

Need constantly exists for converters with higher resolution, faster conversion speed and lower power dissipation. High-speed analog to digital converters (ADC’s) have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately, flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADC’s unsuitable for high-resolution applications. This paper demonstrates a simple technique to reduce comparator requirement of 8-bit flash ADC that requires as few as 65 comparators for 8-bit conversion. In this approach, the analog input range is partitioned into 64 quantization cells, separated by 63 boundary points. A 6-bit binary code 000000 to 111111 is assigned to each cell. A 8-bit flash converter requires 256 comparators, while proposed technique reduces number of comparator requirements to 65 for 8-bit conversion.
DOI: 10.17762/ijritcc2321-8169.1507110