Design of a High Speed Serializer, Timing Analysis and Optimization in TSMC 28nm Process Technology
Main Article Content
The use of serializers and deserializers in SerDes devices is a compulsory requirement for chip to chip communication. They are useful in converting parallel to serial data and vice-versa. Mutltiple SerDes devices are housed in a single package. In this paper, a high speed serializer targeted for speeds as high as 20Gbps is proposed and implemented. This is designed primarily for SerDes devices for chip to chip communication. The serializer is designed to facilitate high speed transfer data rates. This design employs differential logic implementation for the circuit, so as to owe high speed operation when compared to single ended implementation. The custom circuit design simulations are compared against standard library files generated by LIBERATE tool. Also Timing fixes were done using Synthesis flow by writing the RTL code for custom top module design and feeding it to DC and IC Compilers.
How to Cite
, N. S. D. N. K. R. “Design of a High Speed Serializer, Timing Analysis and Optimization in TSMC 28nm Process Technology”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 3155-60, doi:10.17762/ijritcc.v3i5.4409.