Implementation of SystemVerilog Environment for Functional Verification of AHB-DMA Bridge

Abstract

Now day’s functional verification is a very hot topic. With the growing complexity of modern digital systems and embedded system designs, the task of verification has become the key to achieving faster time-to-market requirement for such designs. Verification is the most important aspects of the ASIC design flow. It is estimated that between 40 to 70 percent of total development effort is consumed by verification task. This paper describes the verification of AHB-DMA interface using system Verilog. System Verilog is the special hardware description language used in functional verification. The verification environment designed using System Verilog.
DOI: 10.17762/ijritcc2321-8169.150564