Circuit Design of Programmable Logic and Interconnect Blocks using Spin Transfer Torque RAM for Non-Volatile FPGAs

Abstract

Most of the Field-Programmable Gate Arrays (FPGAs) are currently SRAM based. The conventional SRAM has been the primary choice for memory storage in the Configurable Logic Blocks (CLBs) as well as for the configuration bits of the reconfigurable interconnects. However SRAM based FPGAs are volatile and needs an external non-volatile memory to store the configuration data. Also SRAM leakage currents increases as technology scales towards lower nodes. The use of non-volatile memories such as Spin-Transfer Torque (STT)-RAM helps to overcome the drawbacks of SRAM-based FPGAs without significant speed penalty. In this paper we present the design of simple non-volatile CLBs using STT-RAM technology. For verifying the design these CLBs have been programmed to implement various functions. The design has been simulated and verified using cadence tools in CMOS 40nm technology.