Main Article Content
A low-power and high-speed frequency multiplier for a delay-locked loop-based clock generator is proposed to generate a multiplied clock with different range of frequencies. The modified edge combiner consumes low power and achieves a high-speed operation. The proposed frequency multiplier overcomes a deterministic jitter problem by reducing the delay difference between positive- and negative-edge generation paths. The proposed frequency multiplier is implemented in a 0.13-µm CMOS process technology achieved power consumption to a frequency ratio of 2.9 µW/MHz, and has the multiplication ratios of 16, and an output range of 100 MHz–3.3 GHz.
How to Cite
, P. M. P. R. G. J. (2016). A Low-Power and High-Speed Frequency Multiplier for DLL-Based Clock Generator. International Journal on Recent and Innovation Trends in Computing and Communication, 4(11), 245–251. https://doi.org/10.17762/ijritcc.v4i11.2639