Leakage Reduction Techniques In CMOS Dynamic Logic Circuits

Abstract

The effectiveness of the robust dynamic circuit is degraded much by the increase in leakage current while designing wide fan in circuits. This paper elaborates on the effective leakage reduction techniques which offer lesser delay variability. In order to demote the leakage current, run-time and stand-by techniques are analyzed in detail. Hence, after performing leakage reduction techniques, the sensitivity and robustness of the circuit is analyzed for variations in the process parameters. The spectre simulations are performed on an 8 input NOR circuit using 45-nm technology in ADE-L and ADE-XL environments using cadence® virtuoso. The impact of process variations on delay and power is obtained using Monte Carlo analysis. The analysis demonstrates that the super cut-off technique offers reduced leakage power dissipation of 1.079pw in comparison with the various other techniques. Also, it offers a very minimal delay and power variability with respect to the process variations.