Design of Fast Integer Pipelined Multipliers for CMOS 64-bit Synchronous and AsynchronousLogic with Adaptable Latency

Abstract

Adaptive latency multiplier architecture suited for implementation of multiplier.The architecture combines a second-order carry save and carry select with skipping of the row and split carry using pipelined architecture. The architecture and logic design of CMOS 32-bit synchronous implementation is 2.5 ns. The proposed architecture and VLSI design demonstrates that an adaptive latency multiplier, in either synchronous or asynchronous implementations. This architecture can be used in fast performance multipliers.