An Elementary Proposal on Fault Tolerant Devices for Memory Scenario

Abstract

The paper aims to propose as elementary work on a reliable memory system that can tolerate multiple transient errors in the memory words as well as multiple errors in the encoder and decoder (corrector) circuitry using one class of Error Correcting Codes i.e. type I 2-dimensional Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes and to quantify the importance of protecting encoder and corrector circuitry.