-Memory Computing Based Reliable and High Speed Schmitt trigger 10T SRAM cell design

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Mucherla Usha Rani, N. Siva Sankar Reddy, B. Rajendra Naik

Abstract

Static random access memories (SRAM) are useful building blocks in various applications, including cache memories, integrated data storage systems, and microprocessors. The von Neumann bottleneck difficulties are solved by in-memory computing. It eliminates unnecessary frequent data transfer between memory and processing units simultaneously. In this research, the replica-based 10T SRAM design for in-memory computing (IMC) is designed by adapting the word line control scheme in 14nm CMOS technology. In order to achieve high reading and writing capability, the Schmitt trigger inverter was used for energy-saving and stable use. To speed up the writing process of the design, a single transistor is inserted between the cross-coupled inverters. In addition, to increase the node capacity, the voltage boosting circuitry is emphasized. The adaptive word line control scheme was utilized by integrating the replica column based circuit. The Replica approach regulates signal flow through the core by using a dummy column and a dummy row in RAM. To demonstrate the viability of the suggested design, the simulated outcomes are contrasted with those of existing designs. The various performance metrics examined are Read Static Noise Margin (RSNM), Write (WSNM), Hold (HSNM), Read Access Delay (RAD), Write Access Delay (WAD), Read performance and Write performance the varying supply voltage is evaluated.

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How to Cite
Mucherla Usha Rani, et al. (2023). -Memory Computing Based Reliable and High Speed Schmitt trigger 10T SRAM cell design . International Journal on Recent and Innovation Trends in Computing and Communication, 11(10), 1389–1397. https://doi.org/10.17762/ijritcc.v11i10.8681
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Articles
Author Biography

Mucherla Usha Rani, N. Siva Sankar Reddy, B. Rajendra Naik

*1Mucherla Usha Rani, 2N. Siva Sankar Reddy, 3B. Rajendra Naik

*1Associate Professor,

ACE Engineering College, Jntuh, Medchal, Hyderabad, 501301, India.

*Email: usha.rani1991@gmail.com

2Associate Professor,

Vasavi College of Engineering, Osmania University, Hyderabad, 500089, India.

Email: n.sivasankarreddy@staff.vce.ac.in

3Dean Student Affairs, Osmania University Hyderabad, 500007, India.