Design and Implementation of Hybrid Multiplier for DSP Applications

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Amgoth Laxman, N Siva Sankara Reddy, B Rajendra Naik


In recent decades, there has been a consistent reduction in feature sizes in integrated circuit (IC) technology, leading to the need for increased placement of functional circuits on each chip. When it comes to the design of digital circuits, there is a significant focus on hybrid logic. Hybrid logic is highly regarded due to its ability to consume less power while achieving higher efficiency. Hybrid logic circuits have similarities to complementary metal-oxide-semiconductor (CMOS) transistors, yet possess a reduced transistor count while offering enhanced performance and reliability capabilities. This study examines the modeling and implementation hybrid multiplier with of help of hybrid adder. The functionality of adder is determined with the help of hybrid logic producing XOR/XNOR functionalities in single circuit.    The proposed hybrid Multiplier, which incorporates a hybrid Adder, has been successfully designed and implemented using CMOS 45nm technology and Mentor Graphics software the hybrid transistor logic multiplier demonstrates a decrease in total delay of 60% compared to CMOS.

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How to Cite
Amgoth Laxman, et al. (2023). Design and Implementation of Hybrid Multiplier for DSP Applications. International Journal on Recent and Innovation Trends in Computing and Communication, 11(10), 623–628.
Author Biography

Amgoth Laxman, N Siva Sankara Reddy, B Rajendra Naik

Amgoth Laxman1, Dr. N Siva Sankara Reddy2, Dr. B Rajendra Naik3

1ECE, UCE, Osmaniae University, Telangana, India

2Associate professor

ECE, Vasavi college of Engineering, Telangana, India.


ECE, UCE, Osmania University, Telangana, India