Analysis and Design of Power Gated Low-Power, High Performance Latch Dynamic Double-Tail Comparator

Abstract

This paper introduces an elite, low power dynamic hook comparator making utilization of energy gating system with the end goal of diminished power. The comparator has dependably been a heart of simple to advanced converters in VLSI circuits. The lessening in power utilization of comparator eventually diminishes the power utilization in ADC squares. The proposed configuration has been recreated on Tanner EDA at 180nm TSMC and accomplished up to 15% diminishment in power and 71% lessening on kickback clamour from the traditional plans and in view of the present outcomes and investigation. A new low power, elite comparator is proposed, where the circuit of a dynamic twofold tail comparator with power gating procedure is altered for low-power and quick operation even in little supply voltages. With no troubles in circuit plan and by including couple of transistors, the positive criticism amid the recovery is reinforced, which brings about amazingly lessened defer time. Post-design re-enactment brings about a 180nm CMOS innovation gave the examination comes about successfully. It is demonstrated that in the proposed dynamic comparator both the power utilization, defer time, kickback noise is altogether decreased.