Design & Performance Analysis of 8-Bit Low Power Parity Preserving Carry-Look Ahead Adder

Abstract

In the field of quantum computation, the reversible logic and nanotechnology has gathered a lot of attention of researcher’s in the recent years due to its low power dissipation quality. Quantum computing has been a guiding light for nanotechnology, optical information computing, low power CMOS design, DNA computing and Low power VLSI design. Parity preserving is one of the oldest method for error correction and detection in digital system design. In this paper we proposed two parity preserving reversible 8-bit carry look ahead adder circuits. First circuit is designed usingFredkin Gates and Double Feynman (F2G) Gates, while second circuit is designed using Double Feynman (F2G) Gates and Modified Fredkin Gates. By comparing both circuits, we demonstrate that our second proposed design of reversible parity preserving circuit is optimized in terms of quantum cost and power consumption.