Expanded Noise Margin 10T SRAM Cell using Finfet Device

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Published: Aug 31, 2023
DOI: https://doi.org/10.17762/ijritcc.v11i9s.7959
Keywords:
FinFET, low power, SRAM, stability, Ion/Ioff ratio, Noise margin

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Prashant Udaychand Jain
Research scholar, Department of Electronics and Communication, GLA University, Mathura. U.P., India
Vinaykumar Tomar
Professor, Department of Electronics and Communication, GLA University, Mathura. U.P., India

Abstract

Static random access memory (SRAM) cells are being improved in order to increase resistance to device level changes and satisfy the requirements of low-power applications. A unique 10-transistor FinFET-based SRAM cell with single-ended read and differential write functionality is presented in this study. This cutting-edge architecture is more power-efficient than ST (Schmitt trigger) 10T or traditional 6T SRAM cells, using only 1.87 and 1.6 units of power respectively during read operations. The efficiency is attributable to a lower read activity factor, which saves electricity. The read static noise margin (RSNM) and write static noise margin (WSNM) of the proposed 10T SRAM cell show notable improvements over the 6T SRAM cell, increasing by 1.67 and 1.86, respectively. Additionally, compared to the 6T SRAM cell, the read access time has been significantly reduced by 1.96 seconds. Utilising the Cadence Virtuoso tool and an 18nm Advanced Node Process Design Kit (PDK) technology file, the design's efficacy has been confirmed. For low-power electronic systems and next-generation memory applications, this exciting 10T SRAM cell has a lot of potential.

Article Details

How to Cite
Jain, P. U. ., & Tomar, V. . (2023). Expanded Noise Margin 10T SRAM Cell using Finfet Device. International Journal on Recent and Innovation Trends in Computing and Communication, 11(9s), 767–776. https://doi.org/10.17762/ijritcc.v11i9s.7959
Issue
Vol. 11 No. 9s (2023)
Section
Articles

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