Design of Digital Frequency Synthesizer for 5G SDR Systems

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Digital frequency synthesizers
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Published: Dec 31, 2022
DOI: https://doi.org/10.17762/ijritcc.v10i2s.5906
Keywords:
SDR system, Frequency synthesizer, Phase locked loop, ADPLL

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Vijaya Bhaskar C.
Research scholar,Department of ECE JNTUA,Ananthapuramu Andhra Pradesh, India.
P. Munaswamy
Dean & Professor, Department of ECE IARE,Hyderabad. Telangana,India

Abstract

The previous frequency synthesizer techniques for scalable SDR are not compatible with high end applications due to its complex computations and the intolerance over increased path interference rate which leads to an unsatisfied performance with improved user rate in real time environment. Designing an efficient frequency synthesizer framework in the SDR system is essential for 5G wireless communication systems with improved Quality of service (QoS). Consequently, this research has been performed based on the merits of fully digitalized frequency synthesizer and its explosion in wide range of frequency band generations. In this paper hardware optimized reconfigurable digital base band processing and frequency synthesizer model is proposed without making any design complexity trade-off to deal with the multiple standards. Here fully digitalized frequency synthesizer is introduced using simplified delay units to reduce the design complexity. Experimental results and comparative analyzes are carried out to validate the performance metrics and exhaustive test bench simulation is also carried out to verify the functionality.

Article Details

How to Cite
Bhaskar C., V. ., & Munaswamy, P. . (2022). Design of Digital Frequency Synthesizer for 5G SDR Systems. International Journal on Recent and Innovation Trends in Computing and Communication, 10(2s), 07–13. https://doi.org/10.17762/ijritcc.v10i2s.5906
Issue
Vol. 10 No. 2s (2022): Computer Science Applications: Innovation and Trends
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Articles

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