Design of High Speed Carry Select Adder using Spurious Power Suppression Technique

Abstract

Design of a compact, power efficient and high speed digital adder is one of the most extensive research area in VLSI Design. One of the goals is to increase speed which can be achieved by reducing the propagation delay. Carry Select adder (CSLA) is the most demanding adder which is utilized in data processing systems to achieve fast arithmetic results. Still there is scope for reducing the power consumption, area and delay in the existing designs of CSLAs. In this paper, an easy and competent technique has been used to achieve the same which includes designing of SPST based carry select adder comprising of detection unit and signed extension circuit. Adders being the most important building block of multiplier, will also enhance its performance.