Advanced Shift Register Design Using PSDRM Reversible Logic

Abstract

Reversible logic is one of the most important issues at the moment, with the different areas like low power CMOS devices, quantum computing, nanotechnology, cryptography, optical computing, DNA Computing, digital signal processing (DSP) etc. This can be achieved using reversible logic. The main purpose for designing reversible logic is to minimize cost and throughput. Reversible logic considered as a computing model in which there is one-to-one scaling between their input and output. Power distribution is considered as one of the most important aspects while designing circuit. Reversible logic has become an encouraging technology in low power circuit design. That's because back logic uses only very less power, thus resulting in reduced power dissipation. In this report, we proposed a new reversible gate, and with the help of this gate we have designed our asserted D flip-flop by using the two reversible gates i.e. by using Fredkin and Feynman Gate. The proposed design is better in terms of the average power consumed, number of gates and garbage output than existing. In Shift Register, we introduce a reversible D flip-flop by using FRG and FG gate in the place of existing D flip-flop which used Sayem Gate. The asserted design consumes less energy compare to traditional circuitry. Here we use Pseudo expressions (PSDRM). By using this technology there is an improvement in the factors, such as number of transistors, garbage output, quantum cost and power.