Designing Techniques for Low Power Multipliers: A Review

Abstract

Multipliers are fundamental building blocks of all DSP applications. Design of low power, high speed multipliers is carried out to reduce latency and power dissipation of a processing system because switching and critical computations of a multiplier are high, compared to other data path units of a processing architecture. In recent years, a few techniques have been developed that enhance power for accuracy by removing or rearranging multiplier?s blocks. Choosing the proper technique and implementing it can make a big difference in the power dissipation. This is important for low-power battery-operated devices, where longer battery life could be preferred to higher output accuracy. To enhance speed many changes have been made over the existing booth algorithm. In this paper, a simplified comparative study has been presented among SPST based Wallace tree multipliers and other low power multiplier techniques.