HDL Design for Peta Hertz Clock based 2e31-1 Peta Bits Per Second (Pbps) PRBS Design for Ultra High Speed Applications/Products

Main Article Content

Prof P. N. V. M Sastry, Prof. A. Rajaiah, Prof. Dr. D. N. Rao, Dr S. Vathsal

Abstract

The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of Peta Bits Per Second P.b.p.s (Peta Bits Per Second) Data Rate 2e31-1 Tapped PRBS Pattern Sequence. The P.R.B.S is Designed by using L.F.S.R Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points as per C.C.I.T.T I.T.U Standards. R.T.L Design Architecture Implemented by using V.H.D.L &/ Verilog H.D.L, Programming & Debugging Done by using Spartan III F.P.G.A Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O.
DOI: 10.17762/ijritcc2321-8169.150838

Article Details

How to Cite
, P. P. N. V. M. S. P. A. R. P. D. D. N. R. D. S. V. “HDL Design for Peta Hertz Clock Based 2e31-1 Peta Bits Per Second (Pbps) PRBS Design for Ultra High Speed Applications/Products”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 8, Aug. 2015, pp. 5256-8, doi:10.17762/ijritcc.v3i8.4826.
Section
Articles