HDL Design 2e10-1 Peta Bits Per Second (P.b.p.s) P.R.B.S I.P Core Generator for Ultra High Speed Wireless Communication Products

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Prof P. N. V. M Sastry, Prof. A. Rajaiah

Abstract

The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of 1 P.b.p.s Baud Data Rate using 2e10-1 Tapped P.R.B.S Pattern Sequence. The P.R.B.S is Designed by using L.F.S.R Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points as per C.C.I.T.T I.T.U Standards. R.T.L Design Architecture Implemented by using V.H.D.L &/ Verilog H.D.L, Programming & Debugging Done by using Spartan III F.P.G.A Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O.
DOI: 10.17762/ijritcc2321-8169.150837

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How to Cite
, P. P. N. V. M. S. P. A. R. “HDL Design 2e10-1 Peta Bits Per Second (P.b.p.S) P.R.B.S I.P Core Generator for Ultra High Speed Wireless Communication Products”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 8, Aug. 2015, pp. 5252-5, doi:10.17762/ijritcc.v3i8.4825.
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