High Speed Modified Booth’s Signed 64x64 Bit Multiplier Using Wallace Structure by Radix-32

Abstract

The Main objective of the implemented work is completely based on enhancing speed performance multiplication process using radix-32 modified Booth algorithm and Wallace Tree Structure. It is designed for fixed length 64x64 bit operands. In Wallace structure, 3:2and 4:2 Compressors are used which accumulate the partial products. The implemented modified Booth multiplier is verified and advantages over the existing multiplier are quantitatively analyzed. This implemented multiplier provides less delay 0.238 ns. Many researchers had been worked and presented the modified booth multiplier with optimized delay. In this paper, it has been shown that the implemented 64 bit multiplier provides better delay in comparison with those existing papers. A VHDL code has been written and successfully synthesized and simulated using Xilinx ISE 13.1 simulator software. Also partial products which are generated are less as compared to conventional multiplier. No. of logic blocks required for fast multiplication process has been reduced in terms of no. of slices in comparison with previous ones.
DOI: 10.17762/ijritcc2321-8169.1507121