UVM Based Verification of CAN Protocol Controller Using System Verilog
Main Article Content
Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Gordon Moore. The industry is migrating towards leading edge nodes, which can hold more than 100 Million gates. The chip makers want to pack as many functions possible in their SoCs and provide as many feature additions to gain market share. And, of course, all of those features need to be verified. Verification is currently the largest challenge facing the semiconductor industry in keeping pace with both the customer demand for features and our technical ability to add millions of gates to our chips. Verification quality is a must for functional safety in electronic systems. This paper describes the verification of CAN Protocol Controller using System Verilog. The CAN Controller functions as the interface between an application and the actual CAN bus. Taking this need in consideration, this paper describes flow from specification extraction to development of verification environment.
How to Cite
, S. L. M. A. P. “UVM Based Verification of CAN Protocol Controller Using System Verilog”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 2898-02, doi:10.17762/ijritcc.v3i5.4358.