Statistical Static Timing Analysis for Performance of Logic Gates

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Anil Wanare, Bhushan Malkapurkar


In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This paper proposes the new model for gate delay propagation using the Statistical Static Timing Analysis and the results of it are compared with another modelling called as Monte-Carlo analysis. The proposed model uses Statistical analysis to find accurate propagation delay of the logic gates with reduced simulation time for 16nm technology.
DOI: 10.17762/ijritcc2321-8169.150579

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How to Cite
, A. W. B. M. “Statistical Static Timing Analysis for Performance of Logic Gates”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 2862-5, doi:10.17762/ijritcc.v3i5.4349.