VHDL Implementation of Fastest Braun’s Multiplier
Main Article Content
Multiplication is an essential arithmetic operation for common Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. To decrease computational delay and improve resource utilization carry look-ahead adder circuit are use and Braun’s-architectures multiplier is compared with its conventional architectural.
How to Cite
, R. K. D. P. K. “VHDL Implementation of Fastest Braun’s Multiplier”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 2843-6, doi:10.17762/ijritcc.v3i5.4344.