Development of UVM based Reusabe Verification Environment for SHA-3 Cryptographic Core

Abstract

In this work, an industry standard methodology for ASIC verification domain, SystemVerilog (SV) with Universal Verification Methodology (UVM) is introduced with its features and application to Keccak SHA-3 Cryptographic Core. The ASIC verification flow for SHA-3 core is followed with creation of UVM based verification environment. By application of UVM on the core, horizontal and vertical re-use can be achieved in standard projects. Proposed verification environment uses OOPs concepts from SV UVM to develop layered testbench. In this approach initial learning curve is slow, considering overhead to learn new verification methodology. But, once full fledge working environment is created, re-usability feature from SV UVM can be achieved with less amount of time. Also coverage results give effectiveness of the proposed verification environment.
DOI: 10.17762/ijritcc2321-8169.150571