USRP N210 FPGA Loop Back System
Main Article Content
The USRP™ (Universal Software Radio Peripheral), provides users worldwide to address a broad range of research, industrial, academic and defense applications. The Universal Software Radio Peripheral is developed for RF application, and provides options for GPS Disciplined Synchronization, MIMO configurations and embedded systems. Ettus Research introduced number of USRPs with different FPGA in it. Different USRP have different FPGA but they have similar TX and RX chain in it. Day by day Ettus research provide USRP with large FPGA and FPGA codes open so that users can implement their own modules in FPGA and test it. This paper focused on USRP N210 having Xilinx Spartan 3A DSP FPGA. In USRP 1 they provide loopback system but in current USRP no loopback available. If loopback is available then user can test their module at two stage: 1) after ADC/DAC module and 2) after DDC/DUC module. This paper describes the loopback system at two different stage: 1) after ADC/DAC and 2) after DDC/DUC in USRP N210 FPGA.
How to Cite
, S. S. P. B. G. “USRP N210 FPGA Loop Back System”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 2816-9, doi:10.17762/ijritcc.v3i5.4338.