Verification of AHB Protocol for AHB-Wishbon Bridge using SystemVerilog

Abstract

Verification is the process to demonstrate the functional correctness of design and checks that a product or system meets a set of design specifications. This paper implements is a novel approach to enable data transfer between two different bus architectures, AHB and WISHBONE which have different functionalities and characteristics. The coding for this module is designed in the SystemVerilog HDL and simulated in Questa Sim 10.0b. The Communication is done with AHB as Master and WISHBONE as Slave, hence, achieve error free data transfer between the two different bus architectures. The DUT has been verified for all possible test cases.
DOI: 10.17762/ijritcc2321-8169.150565