Design and Implementation of High-Speed Data Transmission on Multi-Gigabit Transceivers in Spartan 6 FPGA
Main Article Content
This paper gives the design of link where the parallel digital data are transmitted serially at the rate of 3.125Gbps on the Spartan 6 evaluation board. The implemented design is to test Aurora 8b/10b protocol in order to transfer 16-bit parallel data serially over the fiber optic cable in full duplex mode. The 16-bit Parallel data are transmitted and received by the Serialized/De-serialized (SERDES) using Multi-Giga bit transceiver (MGT) at the clock rate of 156.25MHz.Aurora protocol converts the parallel data to serial and serial to parallel. The proposed design is simulated in Xilinx 14.2 and implemented on Spartan 6 FPGA. The serial data are transmitted at the rate of 3.125Gbps over the fiber optic link.
How to Cite
, U. J. V. M. J. S. “Design and Implementation of High-Speed Data Transmission on Multi-Gigabit Transceivers in Spartan 6 FPGA”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 2732-5, doi:10.17762/ijritcc.v3i5.4319.