Design of Quaternary Arithmetic Unit in Standard CMOS

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Nikita C Band, Prof. A. U. Trivedi


The multiple-valued logic (MVL) plays very important role in VLSI circuit design. The number of interconnections is reduced by using Quaternary logic than binary logic. In this paper we present the design of a prototype implementation and experimental results. Quaternary converter circuits are designed by using down literal circuits (DLC). Addition, Subtraction and multiplication i.e. arithmetic operations in Modulo-4 and in galois field logic are design and simulation results are shown in this paper by using Quaternary logic. Schematic of the design is done through S-SPICE. Simulation result is shown in Tspice. Tanner has created a software platform that is cost-effective and easy to use.
DOI: 10.17762/ijritcc2321-8169.150541

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How to Cite
, N. C. B. P. A. U. T. “Design of Quaternary Arithmetic Unit in Standard CMOS”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 2695-01, doi:10.17762/ijritcc.v3i5.4311.