Architecture and Design of Generic IEEE-754 Based Floating Point Adder, Subtractor and Multiplier
Main Article Content
The Floating point numbers are being widely used in various fields because of their great dynamic range, high precision and easy operation rules. In this paper, architecture of generic floating point unit is proposed and discussed. This generic unit is compatible with all three IEEE-754 binary formats. Further based on this architecture, floating point adder, subtractor and multiplier modules are designed and functionally verified for Virtex-4 FPGA. The design is working properly and giving accurate result up to the last point.
How to Cite
, S. D. K. R. P. “Architecture and Design of Generic IEEE-754 Based Floating Point Adder, Subtractor and Multiplier”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 2690-4, doi:10.17762/ijritcc.v3i5.4310.