FPGA Implementation of Area, Delay and Power Efficient Carry Select Adder Architecture Design
Main Article Content
The arithmetic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed. CSLA have great scope by reducing area, power consumption delay. However the regular CSLA is still area consuming due to dual RCA structure, for reducing the area The CSLA can be implemented by using single ripple carry adder (RCA) and BEC converter. In this paper, we present an innovative CSLA architecture which replaces the BEC using D-latch. Substantiation of proposed design is done through design and implementation of 16-bit adder circuit. Simulated result shows that the proposed architecture achieves two advantages in terms of area and delay. Implementation is done in Artix7 FPGA kit. For simulation Xilinx ISE 14.7 is used.
How to Cite
, K. R. K. S. K. A. G. “FPGA Implementation of Area, Delay and Power Efficient Carry Select Adder Architecture Design”. International Journal on Recent and Innovation Trends in Computing and Communication, vol. 3, no. 5, May 2015, pp. 2537-40, doi:10.17762/ijritcc.v3i5.4280.