Design and Implementation of Rijindael’s Encryption and Decryption Algorithm using NIOS-II Processor

Abstract

One of the foremost vital problems in communication customary is that the secure transport protocols. This paper can offer a doable resolution for Rijindael’s encryption and decoding algorithmic program using NIOS II processor, provided by ALTERA to be enforced in FPGA. We are going to see the performance of Rijindael’s AES using NIOS II/e (economic), NIOS II/s (standard) and NIOS II/f (fast). The FPGA has the potential of data processing and hardware modification. The NIOS II is a versatile embedded processor family that represents high performance, lower overall cost, power consumption, complexity combining several functions into one chip. The look of the Rijindael algorithmic program supported “NIOS II + FPGA” are able to do a better processing speed whereas it occupies comparatively low resources. The AES algorithmic program is written in VHDL and is interfaced with the system using general purpose input and output (GPIO) and also the management part is enforced in software in NIOS II integrated development environment (IDE). The implementation is completed on Cyclone II FPGA kit.
DOI: 10.17762/ijritcc2321-8169.1604132