Low power FIR filter design using Graph Based Algorithm

Abstract

Digital filters are a very important part of DSP. In fact, their efficient performance is one of the key reasons that DSP has become so popular. In this paper, we designed an FIR filter using graph based algorithm. Common Sub expression Elimination (CSE) algorithm has a drawback that, it defines the constant in number representation such as CSD (or) MSD, binary. But, when implementing Graph Based (GB) algorithm, it is not restricted to any number of representation of constant. By reducing the height of the tree structure, the numbers of adders are reduced. It reduces the area and power than existing one. The implementation of GB Algorithm is done by Verilog.
DOI: 10.17762/ijritcc2321-8169.150369