Impact of LFSR Seeding on the Test Pattern Generator in BIST

Abstract

This paper considers the problem of minimizing the power required to test a BIST based combinational circuit without modifying the test pattern generator and with no extra area or delay overhead. The objective of this paper is to analyze the impact of the polynomial and seed selection of the LFSR on the power consumed by the circuit. It is shown that proper selection of the seed of the LFSR can lead to significant decrease in the power consumption of the BIST sessions. For this purpose, a Bit Flipping LFSR is used as a test pattern generator in the BIST design. Experimental results using the ISCAS benchmark circuits are reported, showing variations of the seed selected for the LFSR, the power consumed is ranging from 5.5% to 13.5%.