Low Power Design Of Asynchronous Fine-Grain Power-Gated Logic

Abstract

In technology improvement power dissipation has one of the major factor well known short circuit dissipations, leakage dissipations and dynamic switching dissipations are major power dissipation sources of CMOS Chips. For reducing power dissipation in CMOS logic blocks various techniques were there among these techniques most effective new technique implemented with low power dissipation. That is “low power design of Asynchronous fine-grain power gated logic”(LPAFPL). Low power AFPL is a new logic family. It consist of ECRL (efficient charge recovery logic gate), Pipeline system, C-element and Partial Charge Reuse mechanism (PCR). Each pipeline stage is comprised efficient charge recovery logic gate gains power and it is became active when useful computations are there and does not requires power at idle stage. Thus gives negligible leakage power dissipation. PCR is the output node of the ECRL logic, To evaluate the CMOS logic circuit level. Then it automatically reduced the power dissipation in complete evaluation of CMOS circuits.