VLSI Implementation of Encoder and Decoder for Advanced Communication Systems

Abstract

Forward Error Correction (FEC) schemes are an essential component of wireless communication systems.Present wireless standards such as Third generation (3G) systems, GSM, 802.11A, 802.16 utilize some configuration of convolutional coding. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. The Viterbi algorithm is the most extensively employed decoding algorithm for convolutional codes which comprises of minimum path and value calculation and retracing the path. The efficiency of error detection and correction increases with constraint length. In this paper the convolutional encoder and viterbi decoder are implemented on FPGA for constraint length of 9 and bit rate ½.