Design of Wallace Tree Multiplier with Power Efficient Adiabatic Logic

Abstract

The objective of this project is to design high performance arithmetic circuits which are faster and have lower power consumption using a new adiabatic logic family of CMOS and to analyze its performance for sequential circuits and effects upon cascading. It commencement on evaluation of a computational block before its evaluation phase begins, and quickly performs a final evaluation as soon as the inputs are valid. This adiabatic logic family is best suited to arithmetic circuits because the critical path is made of a long chain of cascaded inverting gates.In this paper we are going to design Wallace Tree Multiplier using full adder structure with adiabatic logic. As the major advantage of this logic which is higher speed and low power consumption is observed upon cascading, it is most suitable for arithmetic circuits.