Partial Address Field Architectures For Energy Efficient Caches in Embedded Systems - A Review

Abstract

Most of the embedded processors utilize cache memory in order to minimize the performance gap between memory systems and processor. In embedded systems caches are normally implemented along with processors in one IC. The power consumed by the cache system constitutes the major fraction of the power dissipated by the embedded processors. With increasing computational demands on embedded processors, set-associative caches are being used. In larger caches the major portion of power consumption occurs in address decoding including tag comparisons. Set-associative caches consume larger energy as compared to the direct mapped caches as i) set-associative caches have greater tag bits, ii) they have parallel organization of tag arrays, and hence parallel tag comparison dissipates more energy. It is further analyzed that not all the tag bits are necessary for a cache configuration to achieve a normal performance in terms of hit rate. Hence, architecture with reduced but optimum number of tag bits is possible, which would consume lesser energy. Currently lot of research is going on to find newer architectures for Cache designs so as to give better energy savings. In this paper it has been shown that there are various considerations while designing the cache architecture and a review work done is shown on existing power reduction and performance enhancement schemes in cache architecture design.