Design of High Speed Comparator

Abstract

A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog - to - digital converters with High Spee d, low power dissipation and immune to. Back - to - back inverter in the latch stage is replaced with dual - input single output differential amplifier. This topology completely removes the noise that is present in the input. The stru cture shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current source ces, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, n oise immunity.