Design of 16-Bit Quaternary adder using Various Encoding Techniques

Abstract

Design of binary circuit is restricted by the necessity of the interconnection. A conceivable arrangement could be touched base at by utilizing a bigger arrangement of signs over the same chip region. Quaternary outlines are picking up significance from that point of view. In this paper we design two types of full adder based on quaternary logic is proposed which will reduced the parameter such as area, power, and delay. The feature of this full adder is based on one hot encoding technique and binary encoding technique. All the design is using 180nm CMOS techniques. Sum and carry blocks are handled in two separate square controlled by the code generator unit. Plan check will be done by tanner tools.