Design of Reversible Even and Odd Parity Generator and Checker Using Multifunctional Reversible Logic Gate (MRLG)

Abstract

Digital data transmission made more efficient of communication. For error free transmission in the digital communication at the source end used parity generator and at destination used parity checker. This paper proposed design of 3 bit reversible Even and Odd parity generator and checker using the multifunctional reversible logic gate (MRLG). The proposed design is designed and simulated using cadence software.