Validation of Octanary Adders in VHDL

Abstract

Adders being the lowest building block in circuits, if can handle more data then certainly it can lead to smaller Silicon Area, low power consumption & Higher speed which can help in increasing portability in devices. Binary Logic Circuit design is limited by the number of bits that can be handled and interconnections. Multi Valued logic gives an extra dimension and thus extends the binary logic where more than two values can be dealt with. This paper gives the concept of octanary adders, and its simulation on Xilinx ISE Design Studio 13.1