A Novel Approach for Design of Carry Select Adder

Abstract

In VLSI technology smaller area, less power and faster units are the major concern of VLSI circuits. As addition is the basic operation of all computer arithmetic, adders are one of the widely used components in digital integrated circuit design .In many DSP processor digital adders are the fundamental block. The structure of carry propagation adder produces high propagation delay thus it reduces overall performance of DSP processor. Therefore to alleviate this problem carry select adder is used in many computational systems by independently generating multiple carries and then select a carry to generate the sum. The carry select adder uses multiple pair of ripple carry adder for generating carry, hence area and power of the circuit increase. To overcome this problem we proposed a new way to design carry select adder with transmission gates and binary to excess one converter. The area of modified carry select adder is reduced to great extent thus it consumes less power, therefore delay also get decreases.