Design of Pseudo Random Binary Sequence Generator using VHDL

Abstract

Pseudo Random binary Sequence Generator technique are used for various cryptographic applications and for designing encoder, decoder in different communication channel . The implementation of PRBS generator is based on the linear feedback shift register (LFSR).The total number of random state generated by the LFSR depends on the feedback polynomial. It is nothing but a simple counter so it can count maximum of 2n -1 cycle by using maximum feedback polynomial. In this paper, the entire design of the PRBS generator is implemented using VHDL.